The present invention relates to fabricating semiconductor components for microelectronics and/or optoelectronics. More precisely, the invention concerns fabricating and/or preparing thin layers for making such components, by measuring the thickness of the layers and then taking action to adjust thickness in accordance with specifications.
Such thin layers are made at the end of a fabrication facility and include a plurality of successive steps. The SMART-CUT® method is an example of such a method of fabrication. A general description of the method can to be found in the work “Silicon-on-insulator technology: materials to VLS”, 2nd edition by Jean-Pierre Colinge, (see pages 50 and 51 in particular). Such a method enables thin layers and films of semi-conductor material to be obtained. A variant of the method includes the following steps. During a first step, at least one face of a wafer of semiconductor material is oxidized. During a second step, a zone of weakness is created beneath a face of the wafer by ion implantation. During a “bonding”, third step, the face of the wafer is put into close contact with a supporting substrate and is secured thereto. During a fourth step, the assembly including the wafer and the supporting substrate is subjected to treatment suitable for creating detachment in the wafer at the zone of weakness. During a fifth step, finishing techniques are conducted on the implantation face of the portion including the substrate to reduce the defects generated by the detachment, and/or to reduce the level of roughness to a suitably low level.
Examples of finishing techniques can be found in International Application Publication No. WO 01/15215 A1 which teaches a technique implementing annealing, and in International Application Publication No. WO 01/115218 which teaches a technique implementing polishing and oxidizing steps.
The SMART-CUT® method thus makes it possible to make multilayer silicon-on-insulator (SOI) type structures by retaining a layer of oxide as created during the first step on the implantation face of the wafer. Then, during the bonding step, the layer of oxide is interposed between the supporting substrate and the wafer.
FIG. 1 illustrates a particular implementation in steps 101 to 105 of the SMART-CUT® method for fabricating an SOI structure, which are described below.
It should be understood that other types of methods also exist that enable SOI structures to be fabricated. Whatever the type of method implemented, each new step included in a fabrication facility necessarily requires handling of and/or intervention on the layers, thus leading to additional risk of fabrication defects.
One type of fault relates to a layer having a thickness that departs from the thickness specifications required by the manufacturer. Layers can be rejected because of defects resulting in the thickness of the layer not corresponding to the thickness specifications, in particular in terms of mean thickness of the layer, and/or non-uniformity of thickness within a given layer (often referred to as failure to satisfy the requirement for “within wafer” uniformity).
Layers are usually fabricated in batches, and it is also desirable to satisfy specifications for uniform thickness between the various layers of a given batch (referred to as “wafer-to-wafer” uniformity).
The batches may correspond to layers that have been subjected to the same fabricating steps, under the same conditions (same annealing, etc.) Batches may also correspond to a group of layers defined in some arbitrary way, e.g. they may correspond to production over a given time interval (one day or some other time interval). It is often desirable, at the end of fabrication, to achieve the same average thickness for all the layers of the batch (within some given tolerance, which typically is within a few percent).
It is also generally desirable to achieve “batch-to-batch” uniformity between the layers of various batches, when the final thickness specifications (represented by an average thickness value, for example) are the same for the layers of various batches.
Thickness inspection steps implementing techniques for measuring the thicknesses of thin layers are therefore generally associated with certain steps for processing the layers, all along the fabrication facility. These inspection steps imply that layers will be rejected if they present thickness defects that are harmful to the proper operation of future electronic components.
Returning to the example of the main steps in a SMART-CUT® type method for preparing SOI as shown in FIG. 1, the thickness inspection steps are represented diagrammatically by the diamond-shaped lozenges 107. The thickness inspections occur downstream from each step in the method of preparing SOI, such as after the oxidizing step 101; after the ion implantation step 102; after the bonding step 103; after the heat treatment step 104; and after the finishing step 105.
It should be understood that the configuration shown in FIG. 1 is a “maximum” version of the implementation of thickness inspection steps 107. In reality, thickness inspection steps are not associated with each step in the method of preparing SOI, but only with some of the steps. If the thickness measured on a layer is satisfactory, then the layer moves on to the following step. Otherwise the element is rejected and scrapped at 108.
The conventional methods that include multiple layer thickness inspections lead to material being lost, and also to a consequent reduction in the rate of throughput of the fabrication facility. Throughput suffers as a result of the need to very closely inspect the fabrication steps which affect the thickness of the layers.
One solution for reducing those drawbacks would be to eliminate the various successive inspections of thickness, or to relax the constraints associated therewith by including a thickness correcting step at the end of fabrication. It would then be possible to relax the constraints associated with the various steps of the layer fabrication process, thereby simplifying and accelerating the operation of the process. Consequently, it is important to implement methods and apparatuses that correct thickness in a manner that is effective and accurate, particularly since the thicknesses of thin layers are becoming smaller year after year due to layer-preparation technique improvements.
A first attempt at satisfying such requirements is proposed by the so-called plasma assisted chemical etching (PACE) method described in the document “Semiconductor wafer bonding: science and technology”, by Q. Y. Tong and U. Gösele. The main steps of the PACE method are, in outline, as follows. After acquiring thickness measurements of a thin layer by means of an optical reflection technique, a control unit responds to the measurements it receives by deducing specifications for correcting the thickness of the layer. The thickness adjustment apparatus receives the thickness adjustment specifications from the control unit and then corrects the thickness defects of the layer in application of the specifications. The thickness adjustment apparatus implemented by the PACE method uses a plasma assisted chemical etching technique. That technique is based on using a chemical etching technique that is localized relative to the layer.
A tool applying such techniques is thus suitable for removing material from the layer. Since the tool removes material from an area that is much smaller than the area of the layer, thickness adjustment is thus performed locally on the layer. Since the tool is also suitable for moving over the layer, it travels over all or part of the layer following a path that comprises a plurality of sequences, each lasting for a certain length of time.
The layer adjustment specifications previously generated by the control unit define the path sequences and the etching times. Such specifications are directly linked with a map of thicknesses as deduced from the measurements performed on the layer.
This method of thickness reduction thus seeks to apply treatment that is adapted to the thickness characteristics of each fabricated layer, and to perform individual repair operations on each layer.
The PACE method relating to the thickness adjustment apparatus using the plasma assisted chemical etching technique nevertheless suffers from several drawbacks. First, the conditions under which such technology are implemented are highly constraining. The reaction chamber in which etching is implemented is fouled by the etching operations and therefore requires frequent maintenance. Further, the need to establish a vacuum in the reaction chamber is an additional constraint in terms of implementing such a method, since a high vacuum requires large and expensive pumping means, significant sealing means, and high-performance monitoring means. Second, the very principle of moving the tool that removes material over the layer along a path that is associated with locally removing material by etching leads to lengthy and laborious treatment of the layer. Including such a step of treating layers by etching in a facility for mass producing thin layers is therefore difficult since the rate at which thin layers enter and leave the etching chamber slows production down.
Third, plasma assisted chemical etching technology itself suffers from drawbacks, some of which are further amplified when it comes to treating very thin layers. As mentioned above, it is desirable to fabricate layers of ever decreasing thickness, making it more and more important to control the quantity of material that is removed very finely. In particular, exposing a thin layer to a plasma in a highly reactive environment can lead to defects being created in the crystal structure and to charge accumulating within the layer. This is particularly harmful when the layer is thin. This limitation means that PACE applications are limited in practice to layers having an average thickness of more than 1 micrometer (μm).
The resolution of the PACE technique is limited in practice to accuracy over the thickness that is finally obtained that is of the order of a few hundreds of angstroms (Å). This accuracy thus makes it possible to produce layers having thickness of the order of 1 μm with precision of the order of a few percent. However, with very thin layers, where the desired thickness may be of the order of 1000 Å, for example, tolerance of a few percent in the final thickness corresponds to resolution of a few tens of angstroms, and that cannot be envisaged with the above-mentioned PACE technique.
The PACE technique is therefore unsuited to correcting the thickness of thin layers when the mean thickness thereof is less than a value of 1 μm. Lastly, it is very difficult to control the characteristics of the plasma implemented in PACE in such a manner as to treat substrates of large dimensions. It thus appears that the attempted solution corresponding to the PACE method suffers from numerous limitations.
A second attempt at satisfying the need to implement methods and apparatuses for correcting thickness in effective and accurate manner is also known. International Patent publication document no. WO 01/83238 in the name of Epion Corporation discloses an example of the second type of technique.
However in that case also, some of the limitations mentioned above with respect to the PACE technique continue to apply. In particular, the technique proposed by Epion is expensive and complex to implement. It is also necessary in that case to establish a vacuum in the reaction chamber. Another major limitation of the Epion technique is again that individualized treatment is performed sequentially on different zones of a layer, which leads to treatment times that are lengthy. Moreover, this second type of technique does not make it possible to achieve levels of roughness that are small enough for the intended applications, in particular when fabricating SOI.
The term “simultaneously” used herein means that the various zones of the surface of the layer are treated at substantially the same time.
Thus, the various attempts mentioned above suffer from limitations.